RISCVEMU
News
- 2017-08-06:
- added JSON configuration file
- added graphical display with SDL
- added VirtIO input support
- added PCI bus and VirtIO PCI support
- x86: added IDE, PS/2, vmmouse and VGA devices
- added user mode network interface
- 2017-06-10:
- Support of user level ISA version 2.2, priviledged architecture
version 1.10
- 1.4x faster emulation
- Device tree support
- Can be used online
Introduction
RISCVEMU is a system emulator for the
RISC-V architecture. Its purpose is
to be small and simple while being complete. Among its features the
support of 128 bit addressing and 128 bit floating point makes it ready
for the future !
Main features:
- RISC-V system emulator supporting the RV128IMAFDQC base ISA (user
level ISA version 2.2, priviledged architecture version 1.10) including:
- 32/64/128 bit integer registers
- 32/64/128 bit floating point instructions (using the SoftFP Library)
- Compressed instructions
- Dynamic XLEN change
- VirtIO console, network, block device, input and 9P filesystem
- Graphical display with SDL
- x86 system emulator based on KVM using the same devices
- Small code, easy to modify, no external dependancies
- Javascript version running 32 or 64 bit Linux.
Download
RISCVEMU source code: riscvemu-2017-08-06.tar.gz
RISC-V boot loader, Linux kernel and filesystem
with busybox (riscv32 and
riscv64
targets): diskimage-linux-riscv-2017-08-06.2.tar.gz.
Licensing
It is released under the MIT license.
Fabrice Bellard - https://bellard.org/