- Support of user level ISA version 2.2, priviledged architecture
- 1.4x faster emulation
- Device tree support
- Can be used online at vfsync.org.
RISCVEMU is a system emulator for the
RISC-V architecture. Its purpose is
to be small and simple while being complete. Among its features the
support of 128 bit addressing and 128 bit floating point makes it ready
for the future !
- RISC-V system emulator supporting the RV128IMAFDQC base ISA (user
level ISA version 2.2, priviledged architecture version 1.10) including:
- 32/64/128 bit integer registers
- 32/64/128 bit floating point instructions (using the SoftFP Library)
- Compressed instructions
- Dynamic XLEN change
- VirtIO console, network, block device and 9P filesystem
- x86 system emulator based on KVM using the same VirtIO devices
- Small code, easy to modify, no external dependancies
RISCVEMU source code: riscvemu-2017-06-10.tar.gz
RISC-V boot loader, Linux kernel and filesystem
with busybox (riscv32 and
More complete disk images are
available at vfsync.org.
It is released under the MIT license.
Fabrice Bellard - https://bellard.org/